Verneri Hirvonen

FWIW here's a library of AXI4-Lite types, some interconnect, and some peripherals: https://gitlab.com/a-core/a-core_chisel/amba/-/tree/master/src/main/scala/axi4l I agree that it would be a good idea to add the bundle definitions to `stdlib` since...

> I think we should rely on Chisel's implicit clock and reset whenever possible and not artificially limit ourselves. Now that I think about it, another good reason for going...

FWIW here are some benchmarks ran on MacBook Pro (Retina, 13-inch, Early 2015) with 2.7 GHz Dual-Core Intel Core i5. ## brainwhat ``` Benchmark 1: brainwhat mandel.b Time (mean ±...