Chick Markley

Use circt with verilator backend

1

The overall goal is to be able to run chiseltest unit tests with `CIRCT`/`firtool` *instead* of `firrtl` ## This is first step. It does the following - Creates a new...

Update the chisel-lang documentation for this project

3

An update on basic stuff - backends - what they are - how to change them and why - caching - decoupled

Problem is verilator executive attempts to generate cpp file with elaborated dut, do to so it needs widths of all top level inputs but dut has not been run through...

I think the TestBuilder in ChiselScalaTestTester should be doing a makeScope to set up the logging options. Chisel stage does it but I think it's possibly too late. This is...

Look into fsdb support for testers2

1

This issue is a reminder to consider support for `fsdb` as was done in chisel-testers [PR #236](https://github.com/freechipsproject/chisel-testers/pull/236)

Check widths of data being poked into io ports

1

Currently one can poke a number that is too many bits for the input port. This can lead to confusing behavior in verilator. Treadle seems to be relatively immune to...

Test Directory collisions may confuse users

1

A nice feature of Testers2 is that it bases the name of the work directory for a test from the scalaTest test name. This can lead to potential collisions if...

… were just representing shell prompts I changed them to > Also fixed the stale links in readme

The current release version contains a bug that causes a failure in the Risc example test harness The problem is related to the Memory handler in Treadle's handling of memory...

Diagrammer needs flag to allow passing in annotations

2

Some diagrams aren't generated correctly if annotations are not included. This can be caused by DontTouch annotations being not included, cause elements of the hierarchy to be removed