chiselv
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carlosedp
A RISC-V Core (RV32I) written in Chisel HDL
switch to decoder, recode InstructionType uop to OneHot, improve dispatch timing by removing useless Mux. (just a prototype, not guarantee the correctness ;p)
Updates [com.carlosedp:riscvassembler](https://github.com/carlosedp/RiscvAssembler) from 1.1.1 to 1.1.2. [GitHub Release Notes](https://github.com/carlosedp/RiscvAssembler/releases/tag/v1.1.2) - [Version Diff](https://github.com/carlosedp/RiscvAssembler/compare/v1.1.1...v1.1.2) I'll automatically update this PR to resolve conflicts as long as you don't change it yourself. If you'd...
The core generation for FPGA fails due to: - [x] Memory initialization is generated only inside the ifndef SYNTHESIS block #4752 - -> Fixed by https://github.com/llvm/circt/issues/4752#issuecomment-1696021770 - [x] Synthesizing generated...
I'm having a real problem with generating chisel. ``` [bwalker@fedora fusesoc-chiselv]$ fusesoc run --target=ulx3s_85 carlosedp:chiselv:singlecycle INFO: Preparing fusesoc:utils:generators:0.1.7 INFO: Preparing carlosedp:chiselv:singlecycle:0 INFO: Generating carlosedp:chiselv:singlecycle-ulx3s:0 Using build tool from: /tmp/tmp6tyi6ud6/core/mill Working...
Since Chisel/Firtool now requires a synthesis define `ENABLE_INITIAL_MEM_=True` to be able to initialize memories with external files (readmemh/readmems), this define has been added to the chiselv.core file but was not...