Workaround to generate bitstream for Xilinx A7 FPGAs using Symbiflow

[carlosedp]

Since Chisel/Firtool now requires a synthesis define ENABLE_INITIAL_MEM_=True to be able to initialize memories with external files (readmemh/readmems), this define has been added to the chiselv.core file but was not picked by Symbiflow, the toolchain used to generate bitstreams for Xilinx board (like the Arty A7).

I've added a workaround on https://github.com/carlosedp/edalize/commit/4a806a8f719787a13b8e122d59af6def6c4c5879 that allows passing defines in the filelist array.

This can be used until symbiflow has a proper flag for defines which I've sent here: https://github.com/chipsalliance/f4pga/pull/669

There's an issue open on Edalize at https://github.com/olofk/edalize/issues/434.

The workaround can be installed as described in the Readme (added on https://github.com/carlosedp/chiselv/commit/63095e5d9ffde8424a397ebcaa9873693fc23f40).

This could be removed once everything works upstream (Edalize and F4pga PRs).