cappold

Questions about dummy instruction insertion (instructions from if-stage skid buffer can get lost)

4

Hello, we are using IBEX with dummy instruction insertion and are doing formal verification experiments. We have observed that when a predicted branch is in the skid-buffer of the if-module...

Instruction for next program counter after mret executed first before instruction at mret target

2

Hello, we are making formal verification experiments with IBEX and we for example have also found the problem from bug #1462 two days ago, with overwriting the branch mispredict address...