Rémy GIBERT
Rémy GIBERT
if you do: > lda D2.CurrentQTrack > cmp D2.TargetQTrack > bne .3 > > lsr CS if X,Y on > > jsr D2.Wait25600usec > > lda IO.D2.Ph0Off,y > > bcc...
Finally managed to trap this issue in a simple packet trace. Already noticed this behavior while working on complicated TCP code, but this time i'm writing a simple UDP client...
Is there really no way to get VBL still at 50 or 60 Hz while in accelerated CPU speed ?
AppleWin 1.30.14.0 : Why cannot mount 800k image anymore as S7D1 or S7D2 ???
Where could i find documentation to add an ETH driver to support this board ? https://github.com/A2osX/A2osX actually supporting, U1, U2, LANCEGS, SSC/PPP... https://github.com/A2osX/A2osX/tree/master/DRV