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can I generate verilog without sbt ?

12

could someone help me to solve the error ? thanks first. I don't like sbt very much, and try to transform *.scala to *.v as below: 1. download 'chisel3_2.12-3.1.6.jar' from...

Example as following, ``` case class clkDemo(CK: ClockDomain = ClockDomain.current) extends Component { CK.clock.setName("CK") // **position 2** : clock rename in a component val io = new Bundle { val...

ClockDomain.current made CLOCK CROSSING VIOLATION

5

SpinalHDL 1.12.0 There are 2 examples with the SAME function. Eg1. is error and eg2 is OK. This is eg1. ``` case class clkDemo() extends Component { val io =...

How to generate only one block-RAM with byte-writing-mask

7

Creating a memory with byte-writing-mask will synthesize more than one block-ram. It seems such a waste for FPGA resouces. The below will occupy 4 block-ram resouces. ``` case class Test()...

I downloaded bin file from "https://github.com/llvm/circt/releases/download/firtool-1.136.0/firrtl-bin-windows-x64.zip", and I ran "firtool.exe --help" and it prints nothing at windows10.

Failed to run template

4

``` Administrator[3] MSYS ~/chisel-template-main (main) $ sbt [info] welcome to sbt 1.11.0 (Eclipse Adoptium Java 17.0.15) [info] loading settings for project chisel-template-main-build from plugins.sbt... [info] loading project definition from D:\Shdl\msys64\home\Administrator\chisel-template-main\project...