Bernd M.
Bernd M.
Hello Sylvain, I am trying to set the subroutine permission to access "a1.value" in the algorithm "a" without success. ``` algorithm a(input uint1 value) { uint1 local_value = uninitialized; while...
uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board
Hello Sylvain, it looks as if the directions of the signals uart_tx and uart_rx are swapped in the Verilog framework file for the ECPIX5 board. ``` module top( // basic...
Hello, the compiler complaints about missing identifiers, if one includes the unit sysutils for the target "raw". The attached patch fixes the problem for me. [patch_sysutils_raw.txt](https://github.com/tebe6502/Mad-Pascal/files/14923893/patch_sysutils_raw.txt) Regards, Bernd.