Helmut
Helmut
vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules
Hello A suggested solution would be: When parsing the Verilog module, also convert the module name to lowercase and thus resolve the dependencies. Since Verilog is case sensitive, if the...
vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules
We were able to further isolate the problem and have found a workaround. 1. The lower case problem. Insert a dummy modul in the original file. module pf_dpsram_rccs_dummy(); endmodule //...
vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules
Hi see the pull request. #839 only vhdl_parser.py is changed
vhdl_parser.py: components should not be converted to lower-case while instantiating Verilog modules
Hi I find a new effects ------------------------------------------------------------ library design_work; use design_work.PF_DPSRAM_SPECIAL; component PF_DPSRAM_SPECIAL port (...); end component; inRam_0 : PF_DPSRAM_SPECIAL port map( ....); ------------------------------------------------------------ Error: special_storage.vhd(50): (vcom-1195) Cannot find expanded...
Hi Ja, wie gesagt, es währe super wenn man noch eine neue Abteilung neben Kategorie und Baugruppen hätte, die man einblenden/ausblenden kann. Bis dann AsicNet
"Close" war der falsche Button :)
Die Frage ist : Kann man eine partd-db eintraege auf eine andere Weise von a nach b tranferieren.
Datenbankfehler: SQLSTATE[3D000]: Invalid catalog name: 1046 No database selected SQL-Query: SHOW TABLES LIKE ? Parameter: Array ( [0] => users ) Datenbankfehler: SQLSTATE[3D000]: Invalid catalog name: 1046 No database selected...
Hi it's just a warning, but I'm full of them if it comes from generated code or from someone else's. Then I no longer see the warnings that are really...
Hi The main problem is only the big count of the same warning messages. It will be good only suppress the warning that arises because of "use my_lib.all;" and that...