anuejn
anuejn
This PR fixes both issues reported in #546 . Probably there is a similiar issue for ecp5 and ice40 since they both use synplify.
This PR implements individual pin inversion as discussed in RFC #510. I was unsure about changing the internal representation of invert from a single bool to a tuple of bool....
Currently, `ReadPort` and `WritePort` do not respect the clock polarity of the domain. This makes it impossible to use `Memory` with negedge domains. see: https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L281 https://github.com/nmigen/nmigen/blob/d09dedfb485ee94cb492ef8e44ebb87260892532/nmigen/hdl/mem.py#L177
Similiar to #373 platform.add_clock_constraint does not work for instances in lattice diamond. However, the same fix does not seem to be applicable. Do you have any ideas what is going...
Currently, DiffPairs and Pins can be either inverted completely or not at all. This is a problem in corner cases where the hardware inverts some parts of a logical Bundle...
I have a board that has some inverted differential pairs broken out to a connector. The connector is used on several boards and there are daughterboards that can be plugged...
Hey, first of all, thanks for creating chatmosphere :). For me, it would be really nice to be able to use the touchpad to pan normally and zoom only if...
Needed for python dependencies of litex project. The diff hack is to make the text red. I am open to abandon this, if you don't like it ;)
known issues / todos: - [ ] the control daemon does not compile because it still depends on systemd - [ ] the global `bashrc` is not sourced, it needs...