Andrew Butt

Project Proposal: Banked Memory Compiler Backend in MLIR

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**Background** Banked memories, or logical memories that are divided into multiple physical memories, are an important part of achieving high performance FPGA designs. Unfortunately, designing efficient banked memories can be...

Share HW Parameter List Parsing and Printing

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Currently, the code for parsing/printing HW parameter lists is duplicated between the [MSFT dialect](https://github.com/llvm/circt/blob/f1ed562e0e2e3b36ecca51e1d38d069e6836962d/lib/Dialect/MSFT/MSFTOps.cpp#L549) and the [HW dialect](https://github.com/llvm/circt/blob/d8a8bf1296dbc5e740ba2a5e8e265038c49b195d/lib/Dialect/HW/HWOps.cpp#L763). Soon, the [Calyx dialect](https://github.com/llvm/circt/pull/3565) will also need to parse/print HW parameter lists,...

Switch to cached database for routing import

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Signed-off-by: Andrew Butt On our hard drive based storage system, this change decreases the runtime of the import graph nodes step of routing import from over an hour to under...

[fud] xclbin stage should use Xilinx paths, etc., from the configuration rather than hard-coding them

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In [xclbin.py](https://github.com/cucapra/calyx/blob/master/fud/fud/stages/xilinx/xclbin.py) the locations of vivado and v++ are hard-coded instead of being based on some value in the configuration file. This prevents the xclbin stage from working on computers...

Issues with the AXI implementation

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I spent some time today getting the dot-product design working with AXI on real FPGAs. I just manually edited the verilog for now, but I'll document the issues I found...

Add more memory primitives

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Just wanted to start some discussion about adding more memory primitives to Calyx. I will be putting development effort in here, but want some feedback before I really get started....

Formal Verification

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# SymbiFlow Formal Verification Next semester I am doing an independent study on formal verification and am planning on doing a project involving SymbiFlow. My initial thought is performing formal...

When I try to compile the following program (generated by circt and amc): ``` import "primitives/core.futil"; import "primitives/binary_operators.futil"; extern "amc.v" { primitive mem_0_prim[WIDTH, PORT0_SIZE, PORT0_IDX_SIZE, PORT1_SIZE, PORT1_IDX_SIZE](@clk clk: 1, port0_addr0:...

[Calyx] Switch sequential memories to be true single port memories

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Currently, Calyx seq memories have read enable/done and write enable/done signals. This gives the wrong impression that you can perform simultaneous reads and writes, like how you could with a...

Calyx does not correctly support zero bit values

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Zero bit values are useful for cases where memories have a single value, and therefore do not need an address port. Currently memories will need idx_bits to be set to...