Andreas Kurth

Hello @Realhssuperman, thanks for getting in touch with us. > an above link tells that, it is able to manipulate `slv_req_i.w.data` w/o `slv_resp_o.w_ready`. `slv_req_i.w.data` is valid as soon as `slv_req_i.w_valid`...

That is correct, there is a combinatorial path between `slv_req_i.w_valid` and `slv_resp_o.w_ready` in `axi_dw_downsizer`. (That module is not the only one in this repository that has a combinatorial path between...

I would like to keep this issue open until we have implemented the solution described above, if you don't mind.

Hi @bufans, thanks for your questions. > Does this llc_hit_miss unit use one simple state named busy_d to control tag store read? The `busy_q` FF defines if the hit-miss unit...

> Thinking about it a bit more (and dumping it here), we probably want to limit some paths through the crossbar and to make it a bit simpler. For example...

Okay, I have added a `Connectivity` parameter that allows to define how ports are connected: https://github.com/pulp-platform/axi/pull/111/files#diff-5d663a473103fcc1d98bb5efb6115779R176-R197. This implementation simply ties unconnected mux inputs to zero and attaches *error slaves* to...

Thanks for your question, @hdu-lpl. Your observation is correct: `axi_demux_id_counters` currently indicates itself as *full* when the count value for any ID has reached the maximum. This is because there...

Thanks for your feedback, @skokvermon! Supporting Xilinx Vivado Simulator would be desirable. Given the state of SystemVerilog support in the current Vivado Simulator (you tried v2021.2), however, this seems to...

Interesting, thanks for sharing! A `diff` of the design you uploaded to the current code shows that relatively few changes seem to be required. I will go through the changes...

> I will make pull requests. Perfect, thanks! > However one of the changes is that vivado doesn't support empty() method and rand_id_queue in common_verification. The workaround is to change...