Alexandre Isoard
Alexandre Isoard
I find the spec quite sound. But wouldn't it make more sense to have the following pipes: ```c++ using pipe; using pipe; using pipe; ``` all refer to the same...
Hello, Unfortunately, there is no such control, as the rest of the compilation process need those to function properly. You can access a.g.ld.0.bc if you absolutely need to look at...
@keryell for AMD/Xilinx FPGA the data-layout is "little endian, padded and aligned to the 'next' power of two", it helps a lot with vectorization and imposing a strict layout makes...
Also, we are glad that Clang upped the `_BitInt` limit because we have (crazy) users playing around with 8192 bit busses...