Adrian Byszuk

Hello, It seems that there's a problem with the way AXI4 Lite master detects bus idle condition. To trigger this bug it's enough to have this code in your testbench:...

Mixed language simulation doesn't work with Aldec Riviera

24

There's a problem when trying to run mixed language simulation under Aldec Riviera. The problem can be reproduced even with the example in the repo. Apart from the already known...

Aldec Riviera segfaults with cocotb installed by pip

7

Hi, I think I've hit a bug similar to #3078 , but a bit more difficult to trigger. I've got a mixed-language design with both verilog and VHDL modules. For...

Whitespace rules should allow <= operator

1

Currently VSG allows only to configure either a constant or minimum number of spaces. https://vhdl-style-guide.readthedocs.io/en/3.24.0/configuring_whitespace_rules.html#configuring-whitespace-rules There are cases where a maximum number of spaces would be useful as well, i.e....

Better diagnostics when local indent rules don't match default config

1

Hello, I have my local, complete configuration (including both `indent` and `rule` groups). The problem is that often when I update VSG the upstream `indent` config changes in a way...

Python egg for version 3.25 is broken

4

When trying to install new version with `pip3 install vsg==3.25` I get the following error: ``` Defaulting to user installation because normal site-packages is not writeable Collecting vsg==3.25 Using cached...

Wishbone master doesn't handle `wait_until_idle()` properly

2

Hi, Turns out that wishbone master BFM doesn't handle the `wait_until_idle()` call properly. I think it's missing a wait for clock edge. The missing `wait until rising_edge(clk)` code is here:...