Zhiwei

Question about resnet50

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Hi Eric, Since I need to train a ResNet50 with less parameter, i read the code of definition of ResNet in your code. I found that it is pretty different...

test gap between training and test

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Hi~ Thanking for your code firstly ! I use the SyncBatch for training SSD, when training I can get 46.81% mAP after 10 epoches finishes. However, when I use the...

Update torch-xpu-ops pin (ATen XPU implementation)

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73 new ATen operators/variants are added in the pin update. 16 new unit tests ported to enhance functionality coverage. Aligned source file directory structure with ATen native. Fixed corner case...

[Intel GPU] qconv at XPU backend

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# Motivation This PR enables the XPU quantized convolution. The operators it registers are `onednn::qconv_prepack`, `onednn::qconv1d_pointwise`, `onednn::qconv2d_pointwise`, `onednn::qconv3d_pointwise`. We share same operator schemas as Intel CPU backend as both would...

[Intel GPU] Enable fp64 GEMM

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Stack from [ghstack](https://github.com/ezyang/ghstack) (oldest at bottom): * __->__ #140677 cc @jgong5 @mingfeima @XiaobingSuper @sanchitintel @ashokei @jingxu10 @gujinghui @EikanWang @fengyuan14 @guangyey

[Intel GPU] Docs of XPUInductorQuantizer

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# Description Add tutorials for XPUInductorQuantzer, which serves as the INT8 quantization backend for Intel GPU inside PT2E.