Vicidomini Lab issues

Repositories
Issues
Comments

Results 1 issues of


                                            Vicidomini Lab

Registers ending with a whitespace are not shown correctly on the registers.keys()

When a FPGA LabView code has been compiled with a register with a name ending with a whitespace like( `"MyRegister " `) is not correctly reported in session.registers.keys() . `print(session.registers.keys())`...