Yuanjing Cai
Yuanjing Cai
Can the model run with CPU on a laptop? (intel i7-10510U) If so, how to modify the code to be compatible with CPU? Thanks in advance!
According to debug-spec (table 5.1) https://github.com/riscv/riscv-debug-spec/blob/e3e408ccddbde81fc3511bca3de9751c3162f5e9/trigger.tex#L50-L68 In debug mcontrol register, action can't be set to 1 when dmode=0, but spike didn't implement this. Currently spike can write action to 1...
In type 2 trigger (address match control), when set one breakpoint with tselect=0 and chain=1, another with tselect=1 and chain=0, the trigger should only fire satisfying both breakpoint settings, according...