Roberto Beccherle

There is a non working ink in this page. Style lint rule development guide points to [Wrong link](https://github.com/chipsalliance/verible/blob/master/verible/doc/style_lint.md) but should point to [Correct link](https://github.com/chipsalliance/verible/blob/master/doc/style_lint.md)

Hi, just observed that the extension does not recognize a module input in SystemVerilog if it is defined as: `input wire logic Clock;` An example follows. This syntax is perfectly...