Robert Rostohar

> The spec says: "The target writes data to SWDIO on the rising edge of SWDCLK. The target reads data from SWDIO on the rising edge of SWDCLK." I guess...

I2C Interface expects that the address is the actual slave address (7-bit or 10-bit). User application does not need to handle the address translation (R/nW bit). It seems that the...

"__ldrex" and "__strex" were Arm Compiler 5 Intrinsics and later deprecated (5.06). They are not available for GCC. Since there was no better handling for exclusive access in RTX4 at...

Hi @DanielMtzNXP, The EMAC driver for iMXRT1064 (EMAC_iMXRT1064.c) in Keil.iMXRT1064_MWP_V1.5.1 pack is based on the fsl_enet driver 2.5.4 from NXP.MIMXRT1064_DFP.15.1.0 pack (SDK package V2.12.1). This EMAC driver is no longer...

Hi, As you have already figured out for RTX5, when a thread starts there is no stack frame on top of the stack left and the register LR contains the...

Hi Udo, Sorry for the longer response time. We have analyzed the issue again and tested the possible solutions. Using a thread entry wrapper (with the self-terminating behavior) sounds the...

Thread entry wrapper has been added. The problem with GCC stack unwind should be resolved now.

Should be fixed now as suggested. Thanks for reporting it.

It should be still easy to have a pre-built library and adding only the rtx_lib.c with RTX_Config.h and RTX_Config.c (this was always the case). It is true that the GCC/irq_*.S...

Floating point registers are pushed to stack only for threads which used floating point instructions. Registers S0-S15 and FPSCR are pushed by hardware on exception entry and registers S16-S31 by...