Mark Norton

Yep, I just ran into this as well. SPI discontinuous clock with polarity 0 starts low and then has a rising edge mid bit period with no glitch. I think...

I don't think that would work for me. I needed this output:  `sclk` is low and then its first transition is low to high as the capturing edge in...

That is more appropriate, though it still leaves half a phase at the end. I didn't show the entire waveform but there's the usual SPI stuff with chip select deasserting...

Also is there better documentation than https://wavedrom.com/tutorial.html? I did not recognize that `

My thought this morning would be an overloaded or wrapper for CreateClock that takes in frequency as a real instead of period. While I know they're interchangeable, anything that makes...

Yes, my testbenches define a real with the frequency. However as far as overloading it goes, I agree that there's no way for the procedure to know if the real...

I have been expressing as a real in Hz in my wrapper. That most directly converts to period without any unit shifts. Ultimately we need time units for wait statements....

I forgot that CreateClock took period as a time type so I agree that there's no trouble with type resolution if frequency to be delivered as a real. As for...

@saltsucker I can do a similar successful invocation with `vscode-dark-plus-theme`. It also works fine and just as before. I looked through `gruvbox`'s timeline and the variable `use-package` catches as void...

Okay, I think this one is not currently possible without a MAJOR reworking of the syntax file. Basically a capture will not extend over newlines. To make this happen, instead...