Ralender

Results 17 comments of Ralender

simple changes to operation order causes XRT to return incorrect result

> @Ralender . Thanks. This is emulation and I am not quite sure what assumptions emulation makes in regards to xclbin loaded or not prior to buffer allocation. I suspect...

simple changes to operation order causes XRT to return incorrect result

both creating the bo before and after loading the xclbin work on hw. so it is an emulation issue

llvm/sycl/test/xocc_tests/disabled/edge_detection example does not work

I didn't experience any issues in sw_emu but I had the same issue in hw_emu and the linked PR fixes this.

llvm/sycl/test/xocc_tests/disabled/edge_detection example does not work

After some more testing, the issue in sw_emu is still present in on Vitis 2020.1 not in 2020.2.

There are still some xocc and XOCC in sycl/test/lit.cfg.py

I dont see any references to xocc or XOCC in the project anymore. maybe this is outdated ?

Update documentation to new test infrastructure

Documentation about the changes to the test infrastructure were added as part of the XRT PR so this can be closed unless you have other requests.

Simplify difference in `clang/test/CodeGenSYCL/loop_unroll.cpp`

more than a year ago this was need to make all check-clang tests pass. but I have not tested check-clang in a very long time so maybe there are more...

Do not generate DDR bank by default if there is no DDR but HBM

> Hello everyone! I'm having the same issue on a Versal board, is there any update on this? Thanks for your great work! There is a PR(#177) trying to fix...

Build issue with RHEL8

I spend some time looking into what to do with terminate_xsimk. We know it doesn't catch all the cases we would like it to catch and the solution that stopped...

Build issue with RHEL8

The short explication is that the simulator used for hw_emu is often not cleanup by XRT after it is used. and the simulator also has memory leaks which means that...