PeterRugg
PeterRugg
https://github.com/CTSRD-CHERI/cheribuild/blob/36d5dba8e3a9ae67a428eb7469309b19edefdae8/vcu118-run.py#L126 Is this the canonical way to check for something - I have my vivado aliased to vivado_lab, so "which vivado" returns nothing, but running "vivado" works fine. Would it...
We run several instances of QuickCheck in parallel. Recently we noticed that the parallel runs were all producing exactly the same counterexample, and on further investigations, exactly the same tests....
As per a recent spec clarification https://github.com/riscv/riscv-isa-manual/commit/dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e, any load reservation should be cleared on reset, and currently isn't on Sail, which is a problem when running with RVFI_DII. I worked...
Sail crashes when executing a floating point instruction that specifies dynamic (meaning look at `fcsr`) rounding mode, when the rounding mode specified by `fcsr` is one of the two reserved...
This is a somewhat esoteric feature: it might just be us that want it, but thought I'd ask because it seems like it might be simple to add. We're using...
This leads to different values in RVFI. The RISC-V spec allows this behaviour: "simple implementations can ... execute a HINT as a regular computational instruction". Without this feature, such implementations...
(I just want to start by saying how useful the SEED Labs are: I can't imagine how much effort it took to create such a great teaching resource!) In the...