csliu

generate blackbox from verilog

5

generate blackbox as below ``` def main(args: Array[String]): Unit = { val gw1n = GenBlackbox( ivlPathStr = "C:\\iverilog\\bin\\iverilog.exe", srcFileStr = "E:\\working\\working\\SpinalAll\\SpinalHDL\\lib\\src\\main\\scala\\spinal\\lib\\blackbox\\gowin\\gw1n\\prim_syn.v" ) val gw1ns = GenBlackbox( ivlPathStr = "C:\\iverilog\\bin\\iverilog.exe", srcFileStr...

fsdbDump different parament

2

sometimes need different paraments, ```diff @@ -264,7 +264,7 @@ class VCSBackend(config: VCSBackendConfig) extends VpiBackend(config) { |initial begin | $$fsdbDumpfile("$toplevelName.fsdb"); | $$fsdbDumpvars(${config.waveDepth}, $toplevelName); - | $$fsdbDumpflush; + | $$fsdbDumpMDA; |end |endmodule""".stripMargin...

VSC timeScale and timePrecision

1

config ``` 1 ps/100 fs ``` , buf simulate actual ``` 1 ns /100fs ``` ```scala SimConfig .withTimeScale(1 ps) .withTimePrecision(100 fs) ``` because this function use ``` 1ns ``` instead...