Merilix

ZEXALL Test

2

This ZEXALL output doesnt look right. ``` Z80all instruction exerciser msg OK msg OK msg OK msg OK msg OK msg OK msg OK msg ERROR **** crc expected:26db477e found:f13c985a...

monitor.breakWhen one half cycle too late

2

As the title says. The sim should stop on specific signal in order to examine the cpu state when the condition is met. But the sim stops one half cycle...

Subcircuit terminals shared between all Instances.

3

Because the pins of subcircuits are made of named nodes, they are all he same if you have multiple instances. They behave like they are connected parallel. Terminals of a...