MahmoudKMaarouf

Is there a way to make the right parenthesis aligned in instantiations ?

1

Is there a way to make the right parenthesis aligned in instantiations ? **Test case** ```systemverilog // Input to the formatter, preferably a reduced test case. ``` Formatter output: ...

**Test case** ```systemverilog // Input to the formatter, preferably a reduced test case. ```  I expect it to look like this:  Because there is a return between the...

`IFDEFs and such cause incorrect line numbers

4

Placing this on top of code: ``` `ifndef AN_IF_DEF logic [1:0] someVar; `endif ``` will cause the line numbers of the original file to be shifted 1 up (equivalent to...

Linter not working + Extension debug output missing

1

I cannot find extension debug output on VS code terminal output tab. Other extensions have this feature.  Furthermore, modelsim linter does not work despite using same path and command...

Reloading waveforms on GTKWave causes glitch

17

I have installed GTKWave on terminal on my M silicon Mac via the discussion here: (brew command) https://github.com/gtkwave/gtkwave/issues/250 It works great as shown here: Then I alter RTL, rerun Icarus...

Similar issue to https://github.com/mshr-h/vscode-verilog-hdl-support/issues/413 but restarting does not fix the issue [error] [VerilogFormatProvider] Error: spawnSync verilog-format ENOENT /usr2/{...}/vault/verible/bin/verible-verilog-format --indentation_spaces 8 --module_net_variable_alignment align --assignment_statement_alignment align --case_items_alignment align --class_member_variable_alignment align --distribution_items_alignment align...