Keyi Zhang

> Could we do it similar to how we handle loops/if? E.g. task1 = tester.create_task() and task1 provides the tester interface for doing the actions? Seems like we could track...

Usually it's things like ```SystemVerilog @(posedge clk); // or @(value); // or event -> event_var; // and then @(event_var) ``` `@` is more commonly used for clock and events, whereas...

I think writing functional model in python is way easier than C, and probably faster to implement than C++. The prototype I had does the following thing: 1. Take that...

Sounds good. That being said, that project was an experiment to see the potential of DPI-based simulation with Python, so it lacks many capabilities. Here are some enhancement I can...

1. It's the former. I want to load the object during simulation. Since at that point we have lost the python objects, we need a way to reconstruct the functional...

No I haven't. I was caught up by other work. I will try to run it this week.

I think I'm doing something wrong here. Below is the new profile result after the change:  The code is at container `keyi-romantic_ptolemy` on kiwi. To attach the container, you...

Just follow up the conversation about native support for Python models. I started to implement a new Python-to-DPI library that's designed to be framework-independent. I'm still trying to refactor the...

Here is the result after using #288 

This is not a high priority since I've found ways to bypass the parsing verilog by directly exposing module interface to magma. Maybe it's a long-term goal to replace `pyverilog`...