jwhur

Results 15 comments of jwhur

Is there any possibility that ```RegNext(rob.io.flush.valid)``` and ```brupdate.b2.mispredict``` are valid in the same cycle, which makes the mispredict FTQ entry's information writen into the redirect FTQ entry?

Hi, it seems this can actually happen. Here is the testcase and the vcd file. Both `io_redirect_valid` and `io_brupdate_b2_mispredict` signals of `ftq` are simultaneously asserted at 150887 ps. But the...

TLMonitor Assertion failure while running baremetal on BOOM

I could not upload the entire vcd file since it was too big.

TLMonitor Assertion failure while running baremetal on BOOM

I'm sorry for taking your time. It was my mistake, I had modified the binary to return to the supervisor mode. Sorry for the confusion.

Invalid rm in floating point instructions

[test.zip](https://github.com/riscv-boom/riscv-boom/files/4526441/test.zip) like this? It's somewhat awkward but it still works. I included the raw trace of boom (rm field of `fnmadd.s` is 5 which is invalid).

Invalid rm in floating point instructions

Thanks for confirm.

Different result of fsqrt.s Boom vs Spike (Rocket)

fdiv.s also generate result. [test.zip](https://github.com/riscv-boom/riscv-boom/files/5230046/test.zip)

source field in ProbeAckData

Yes, your patch fixes the bug. Now they have same source id. Maybe other components in the hierarchy does not check the source id as seriously, but I couldn't test...

Behavior mismatch between Spike and Boom

Thanks for confirm.

[Bug] jalr to link register

According to the spec, prohibited instruction may leave the cpu state in undefined state. In this case, I think whether asserting exception or not depends on the designer.

[Bug] signed_mul_overflow bug

Modifying the solution, I misunderstood multiply signed overflow. The bug was that the original mul_signed_overflow code does not consider when one of the operands is 0 and the other is...