Harshitha
Harshitha
Wishbone Interface referring to mor1kx.v module.
mor1kx_ctrl_cappuccino.v Code: https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_ctrl_cappuccino.v#L1653#L1656
LRU is not getting correct access information in both cases. Even though there are way_hits as 10 (case 1) and 01 (case 2), this is not updated in the access...
This issue may not be critical from the LRU perspective. All cache hits are not acknowledged to the fetch module, only refill hits and hits during the READ state are...
It's tested in the spr master interface, referring to mor1kx_cpu_cappuccino.v module.
mor1kx_ctrl_cappuccino.v Code: https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_ctrl_cappuccino.v#L1644#L1651