Fernando Flores

Versal ACAP: Tutorial https://github.com/Xilinx/Vitis-Tutorials/blob/2024.1/AI_Engine_Development/AIE/Feature_Tutorials/01-aie_a_to_z giving ERROR:[VPL-60-773] at step 3 when building the link - binary container.

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Hi, I am following the tutorial of AIEs 01-aie_a_to_z: https://github.com/Xilinx/Vitis-Tutorials/blob/2024.1/AI_Engine_Development/AIE/Feature_Tutorials/01-aie_a_to_z . I have done steps 1 and 2 for a TE0950 board instead of VCK190 (But it doesn't matter I...