Jerry

Chipyard TLFIFOFixer documentation confusion

1

The documentation of TLFIFOFixer is as below: _TileLink managers that declare a FIFO domain must ensure that all requests to that domain from clients which have requested FIFO ordering see...

### Discussed in https://github.com/chipsalliance/rocket-chip/discussions/3010 I felt like the following two lines of code is redundant https://github.com/chipsalliance/rocket-chip/blob/00d9e02c1901d0285f22eefec7c25073fb90e4f1/src/main/scala/devices/debug/Debug.scala#L1782 ``` dmInner.module.clock := io.debug_clock dmInner.module.reset := io.debug_reset ``` since the clock domain of **dmInner(TLDebugModuleInner)**...

BaseTile Auxiliary Constructors Bug

5

Inside the `BaseTile` there is `val visibilityNode = p(TileVisibilityNodeKey)` _(it represents the view that the intra-tile masters have of the rest of the system)_. So, conceptually this diolomatic node should...

How are parent and child lazymodule's clock and reset are connected?

2

Every chisel module has implict clock and reset, I wonder if the parent and child's clock and reset are automatically connected? Also, I wonder if parent and child **lazymodule's** clock...

https://github.com/chipsalliance/rocket-chip/blob/66a60e55a18fae859730b01c04450b2da3630e19/src/main/scala/tilelink/Fragmenter.scala#L93 This loc should be removed, because the following loc 97 seems already includes this require condition： https://github.com/chipsalliance/rocket-chip/blob/66a60e55a18fae859730b01c04450b2da3630e19/src/main/scala/tilelink/Fragmenter.scala#L97 @hcook @terpstra

why findFast is fast?

1

Inside the `TLSlavePortParameters` class in tilelink\Parameters, there is one method called findFast as below. ``` def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) Vec(slaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _))) } ``` Recently...

**Type of issue**: bug report **Impact**: lowestIndexFirst behaves wrong and threw firrtl exception under some circumstances. the TileLink arbiter policy `lowestIndexFirst`'s one liner implementation is as follows:https://github.com/chipsalliance/rocket-chip/blob/46c88b71056581a6bf2a0c4febd5ec3d768c6c59/src/main/scala/tilelink/Arbiter.scala#L16 `val lowestIndexFirst: Policy...

Does this line of code make any sense?

1

https://github.com/chipsalliance/rocket-chip/blob/c095dbc8fd7b4097a0540266bac3336fdef4b0d4/src/main/scala/tilelink/BusWrapper.scala#L80 Inside the TLBusWrapper there are methods like `to` and `from`. IMO, using these APIS we can attach other TLMaster or Slaves to this bus. But I think the implmentation...

This line of comment indicates that calling MaskGen with add_lo be 0x3, the lgSize be 0, and beatBytes be 4 will get the result of 0x0001, but when I run...

What is the purpose of mixO and mixI

1

I felt like this is confusing. Taking the mixO as an example, we have a sequence of DO corresponding to the oPorts, but for each DO of the oPorts, we...