Cyril Koenig
Cyril Koenig
Changes: * Re-wired properly the JTAG chain on island disable * Added the safety + spatz config * Corrected pulp cluster CDC constraints * Modified device tree structure to have...
**This PR is based on top of ck/hyperram** * Added VCU118 job to CI * Renamed DTS (removed board name as they are reused) * Added BD constraints for VCU118...
[WIP] this PR aims to test hyper-ram usability on FPGA (both vanilla and BD flow) for basic R/W/X bare metal - Added HYPERRAM flow in CI - Enhanced automatic CDC...
The region at [0x2_8000_0000 ; 0x3_0000_0000[ can be used to bypass the LLC when the LLC is enabled. This is useful to speedup device DMA when LLC is enabled (of...
The VCU118 block design configuration can't use Ethernet for now. This may be a device tree issue, driver issue, or block design parametrization issue. Look into fixing the Xilinx Ethernet...