Christoph Jung

Simple test for masking the shift amount in riscv64 rtype shift instructions

2

Test for [#77](https://github.com/angr/vex/pull/77)

riscv64: shift instructions can behave wrong

5

### Description The RISCV64 ISA specifications say that the shift operations: - sra, srl, sll use the lowest 6 bits of rd2 - sraw, srlw, sllw use the lowest 5...