ChengyueWang

10-GeMM_AIEvsDSP/AIE failed to meet timing

3

For the example: Vitis-Tutorials/AI_Engine_Development/Design_Tutorials/10-GeMM_AIEvsDSP/AIE When I run: make run TARGET=hw ITER_CNT=16 GEMM_SIZE=32 The error occurs saying that the deign failed to meet timing. I am using the Vitis 2023.1 and...

Need to include #include <limits> in the hls-llvm-project/llvm/lib/Support/XilinxPlat/CoreQuerier.cpp

1

Hi Xilinx, Here is a kind reminder that #include is required to be included at the top of the file hls-llvm-project/llvm/lib/Support/XilinxPlat/CoreQuerier.cpp otherwise the project will fail to build with the...

add aie-chess-simulation as examples for single core chess simulation in BFP16 and BF16

1

This PR adds two comprehensive examples demonstrating single-core chess simulation using reduced-precision data types. The examples are located in /tools/aie-chess-simulation/ and include: - simple_test/: Basic AIE chess simulation example for...