Nouri

How to increase the ariane core frequency

5

I want to increase the ariane core frequency ... How can I do that? what is the max frequency reachable ?

Program is halted when running Coremark.riscv

7

Hello I want to run Coremark on the simulator and I used the code here: [riscv-coremark](https://github.com/riscv-boom/riscv-coremark?fbclid=IwAR3_zpPeNgtiOTszdmRNL_mOg5GIeUQUabZK42IX2rCf_N3XUA7gVZqwac4) which generates two version one for baremetal and the other for Linux or pk....

running a program on AWS f1 instance

2

Hello I have read the instructions to work with openpiton on AWS f1 instance and I have some questions: when is it possible to run a precompiled benchmark is necessary...

why is the /piton/design/f1 is empty

1

I trying to build an FPGA image for AWS F1 and I fillowed the exact steps as in readme.md. I got an error message saying that I cannot download submodule...

General Question regarding Openpiton on AWS F1

1

I want to run openpiton image on AWS F1 So my questions are the fiollowing. - Is this FPGA image **agfi-0d87a634f93fe7c83** work with one ariane core ? - How can...

I want to run Dhrystone and Coremark on Ariane on FPGA VCU108. I already found Dhrystone among the submodule riscv-test but Coremark is missing So my question is if I...

error while building riscv-tools

4

Hello I am trying to work with lowrisc So I followed this link : https://www.lowrisc.org/docs/debug-v0.3/zedboard/ So, I have set up the **env** as following : ``` export TOP=$PWD export RISCV=$TOP/riscv-tools/riscv-gnu-toolchain...

Hello I am trying to use update script order to make the zedboard project work with Vivado 2019.1 What I tried is that I copied the two following files to...

Generating designs for PYNQ

1

Can we make ALLO generate Hardware designs targeting PYNQ (Productivity for Zynq) as an Overlay? Any plans to add such a feature? kind regards