CSAL
CSAL copied to clipboard
ARM-software
Coresight Access Library
I have a Cortex-M7 microcontroller (STM32H7), which does not have a filesystem. For tracing the ETB data with `cs_get_trace_data`, a `cs_device_t` object is needed, which needs to be registered on...
Can you recommend a tool for visualizing the traced debug data from the ETB?
Various devices implement a claim tag register which can be used by different agents (e.g. external and self-hosted debug) to negotiate access. Use of these bits relies on agents adopting...
ETS is a configuration option for TMC (Trace Macrocell). It's a bit like an ETR in that it's an ATB sink that writes to a bus, but it has a...
When compiling for BAREMETAL functions the functions under define is in use also (it's in use not only for DEBUG as stated in the comment)
I can't seem to find an example how to setup the ETR buffer, change buffer-size and read from it. Any help would be appreciated.
# Test results: https://github.com/cclauss/CSAL/actions * [Standard GitHub-hosted runners for public repositories](https://docs.github.com/en/actions/using-github-hosted-runners/using-github-hosted-runners/about-github-hosted-runners#standard-github-hosted-runners-for-public-repositories) --> `ubuntu-24.04-arm` * https://github.com/codespell-project/codespell * https://docs.astral.sh/ruff * https://docs.astral.sh/ruff/linter
Remove the Python 3 syntax errors from three files. * `print()` is a function in Python 3. ``` ruff check --ignore=ALL # Returns the files that have syntax errors. uv...
### 1. In `cs_topology_dts.py`: Output on [1]: ``` user@user-desktop:~/Downloads/CSAL/coresight-tools$ sudo python3 cs_topology_dts.py topology.json /* * Device Tree source fragment (for guidance only) */ /* auto-generated */ funnel@0,72010000 { compatible =...
cs_topology_sysfs reads sysfs device nodes and discovers CoreSight devices and also ATB connections. Now that the CoreSight support in the kernel has been extended to support CTI (and CTI connections...