11522514

I don't quite understand the interaction between the firrtl and chiffre libraries or the design parameters I can set. If possible I wouldn't mind setting all resets to be synchronous...

The chiffre transform finished this before emitting the error Time: 871.1 ms Form: UnknownForm ======== Finished Transform VerilogRename ======== ======== Starting Transform VerilogPrep$ ======== ------------------------------------------------- Time: 83.8 ms Form: UnknownForm...