Riscv32e align stack to 4 bytes

[cheme]

To build some riscv32 embeded binary, I had to change the stack alignment.

Not sure if this needs to be in master as no current cpu touch it (at least this PR would be accessible from github if someone else need it).

I was using

    pub const pvm = CpuModel{
        .name = "pvm",
        .llvm_name = null,
        .features = featureSet(&[_]Feature{
            .@"32bit",
            .e,
            .a,
            .m,
        }),
    };

and zig build -Dtarget=riscv32-freestanding -Dcpu=pvm to produce:

Attribute Section: riscv
File Attributes
  Tag_RISCV_stack_align: 4-bytes
  Tag_RISCV_arch: "rv32e2p0_m2p0_a2p1"

But it is not a real cpu (I did not find a convenient way to pass custom features from build.zig to generic riscv).

[alexrp]

Note that you should be able to do something like zig build -Dtarget=riscv32-freestanding -Dcpu=generic_rv32+e (and similarly for other ISA extensions). An extra Cpu entry probably isn't necessary.

[alexrp]

An extra Cpu entry probably isn't necessary.

That said, I do think there's an argument for adding std.Target.Abi tags for RV32E/RV64E (but maybe not until the specifications are actually finalized?). We need to do something similar for other ABI values (ilp32/ilp32f/ilp32d and lp64/lp64f/lp64d), and GCC/Clang support ilp32e/lp64e as -mabi arguments too. I intend to open an RFC issue on solving this soon-ish.

[andrewrk]

Thanks for the patch, and thanks @alexrp for the additional review.