xtensor-stack
Support fixed size SVE
This PR adds fixed size SVE support to xsimd. Client must specify the
vector size in compiler options to enable SVE features.
E.g., -march=armv8-a+sve -msve-vector-bits=128
Make sure the vector size matches the hardware runs the code. Otherwise
the program behaviour is undefined, which may lead to crashes, hangs,
wrong results, even spurious successes.
The SVE ISA in hidden in detail::sve, not meant to be directly used by
client code. To make it explict that we only support fixed size SVE,
trivial aliases like sve128, sve256 are exported for client to use.
They are only defined if client specifies according vector size at
compile time.
CI jobs are added to verify SVE128 and SVE256, which are available on real hardware nowadays. Please note CI runs on x86 host and uses qemu to emulate Arm and SVE instructions.
Closes #786
SVE intrinsics reference FYI. https://developer.arm.com/documentation/100987/0000/
SVE implementation is much concise than other ISA as most SVE intrinsics are overloaded per argument type.
E.g., svadd for all data types, without tedious svadd_u8, svadd_s8, svadd_u16, etc..
cc @JohanMabille , @serge-sans-paille , @pitrou , @guyuqi, @edponce
@cyb70289 Thanks for working on this. PR LGTM! I suggest to also update the README file and possibly add a note that only SVE 128/256 are supported.
Conceptually, xsimd could validate the value of __ARM_FEATURE_SVE_BITS at compile-time. Although as it is currently, the aliases sve128 and sve256 will be undefined for unsupported cases.
