Documenting LVDS input pairs

[DaveBerkeley]

Thanks for the work you've done on this. It has been very helpful.

I'm working on a project that needed an LVDS input to the FPGA. It took me a while to work out where they were connected. I ended up using one of the Lattice pinout spreadsheets (that had some formatting errors in) and writing a script to extract the pairs. I matched these to my Amaranth Platform definition for the v7.2 plus dev board to produce a list of suitable pairs.

These are :

pair ('pmod', 1) J20 K20 pair ('pmod', 1) L18 M18 pair ('pmod', 2) A18 B19 pair ('pmod', 2) A19 B20 pair ('pmod', 3) C1 D1 pair ('pmod', 4) G3 F3 pair ('pmod', 5) K4 K5 pair ('pmod', 6) E5 F5 pair ('pmod', 7) G16 H16 pair ('pmod', 7) H18 H17 pair ('pmod', 7) E18 F18 pair ('pmod', 8) L4 L5 pair ('pmod', 9) R1 T1 pair ('pmod', 9) U1 V1 pair ('pmod', 9) W1 Y2 pair ('pmod', 9) N2 M1

I'm happy to contribute my script and my Amaranth platform file if it would be useful.