DRAMsim3
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umd-memsys
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
In function Controller::ScheduleTransaction, there would be a corner case that the write_buffer is full and the first transaction in write_buffer can not pass the dependency check. When this happens, here...
Hello, I have an issue with RW command scheduling. I am using a DDR3 configuration with transaction queue size of 32 and command queue size of 32. While running simulation,...
Hello! I would like to adopt the DRAMsim3 configuration files as a standard for defining memories in a python-based framework. There is one tiny issue. The python `configparser` has the...
I got a problem when connecting gem5 and Dramsim3 ``` File "configs/example/cmp.py", line 81, in system.cpu[i].workload = process[i] File "/home/mahmood/gem5/src/python/m5/SimObject.py", line 627, in __setattr__ value = param.convert(value) File "/home/mahmood/gem5/src/python/m5/params.py", line...
By gdb debugging for the segmentation fault, I found the index 'i' is over the size of accu_Pmap[case_id] in the basic example. Maybe it's not 'i' increment but 'k' increment....
Hi, I want to reference [http://git.ece.umd.edu/shangli/zsim/tree/master]() for the zsim integration, but the link is not available. Any solution? Thanks.
It seems like `tRFCb` for `BANK_LEVEL_STAGGERED` refresh policy is not applied. Timing parameters for it are defined at [timing.cc:225]( https://github.com/umd-memsys/DRAMsim3/blob/29817593b3389f1337235d63cac515024ab8fd6e/src/timing.cc#L225), but the one of them, `same_rank`, is not used at...
Hi, I want to ask the DRAMSim2. Can we use DRAMSim2 simulate LPDDR4? The paper "A Performance & Power Comparison of Modern High Speed DRAM Architecture" said that DRAMSim2 can...
When running a simulation with a trace file the simulation ends by default as with the `-c 100000` argument. I would like to run for much more many cycles, ideally...
The link in the readme to the sst integration information does not work. This is the link: http://git.ece.umd.edu/shangli/sst-elements/tree/dramsim3 Perhaps you could add the information as a text file to this...
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DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator