Multiple IO ports of same type on FPGA harness

[T-K-233]

Background Work

• [X] Yes, I searched the mailing list
• [X] Yes, I searched prior issues
• [X] Yes, I searched the documentation

Chipyard Version and Hash

Release: 1.10.0 Hash: a6a6a6

OS Setup

https://gist.github.com/T-K-233/38e0aff721f2219a96f116822f9dafda

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

Currently using this HarnessBinder configuration:

class WithArtyUARTHarnessBinder extends HarnessBinder({
  case (th: Arty35THarness, ports: Seq[UARTPort]) => {
    withClockAndReset(th.clock_32MHz, th.ck_rst) {
      IOBUF(th.uart_rxd_out,  ports(0).io.txd)
      ports(0).io.rxd := IOBUF(th.uart_txd_in)
      
      IOBUF(th.jd_3, ports(1).io.txd)
      ports(1).io.rxd := IOBUF(th.jd_7)

      IOBUF(th.ck_io(0), ports(2).io.txd)
      ports(2).io.rxd := IOBUF(th.ck_io(1))
    }
  }
})

and vivado gives the following error message when generating bistream

ERROR: [Synth 8-2716] syntax error near '"DPI-C' [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:3]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:7]
WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:19]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:35]
ERROR: [Synth 8-8896] 'byte' is an unknown type [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:36]
ERROR: [Synth 8-8896] 'bit' is an unknown type [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:38]
ERROR: [Synth 8-8896] 'string' is an unknown type [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:42]
INFO: [Synth 8-10285] module 'SimUART' is ignored due to previous errors [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v:90]
INFO: [Synth 8-9084] Verilog file '/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/SimUART.v' ignored due to errors
INFO: [Synth 8-6157] synthesizing module 'Arty35THarness' [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/Arty35THarness.sv:85]
ERROR: [Synth 8-439] module 'mmcm' not found [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/Arty35THarness.sv:190]
ERROR: [Synth 8-6156] failed synthesizing module 'Arty35THarness' [/home/tk/Desktop/chipyard-fpga/fpga/generated-src/chipyard.fpga.arty.Arty35THarness.TinyRocketArtyConfig/gen-collateral/Arty35THarness.sv:85]

Expected Behavior

Previous working HarnessBinder configuration:

class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
  (system: HasPeripheryUARTModuleImp, th: Arty35THarness, ports: Seq[UARTPortIO]) => {
    withClockAndReset(th.clock_32MHz, th.ck_rst) {
      IOBUF(th.uart_rxd_out, ports(0).txd)
      ports(0).rxd := IOBUF(th.uart_txd_in)

      IOBUF(th.jd_3, ports(1).txd)
      ports(1).rxd := IOBUF(th.jd_7)

      IOBUF(th.ck_io(0), ports(2).txd)
      ports(2).rxd := IOBUF(th.ck_io(1))
    }
  }
})

Other Information

No response

[jerryz123]

Open a PR adding the new HarnessBinder, I can take a look at the branch in that PR