trabucayre
ESP32S3 USB JTAG cable maybe possible
Currently I'm experimenting to get ESP32S3 USB JTAG which is supposedly able to route its native JTAG to external GPIO, if that is possible then we can use it as "cable" to program FPGA.
https://github.com/emard/esp32s3-jtag
Miniature ESP32S3 with USB-C are available for 7$ like XIAO ESP32S3 MINI Mouser P/N: 713-113991114
So here is my wish/idea for openFPGALoader to support it if possible.
openocd driver esp_usb_jtag is fixed here's my source https://github.com/emard/openocd/blob/master/src/jtag/drivers/esp_usb_jtag.c
with this esp jtag it is very fast, speed is comparable to ft2232.
So I tried to make openfpgaloader driver https://github.com/emard/openFPGALoader/blob/master/src/esp_usb_jtag.cpp
but it doesn't work, esp protocol is simple but has details which I don't understant so it's not so easy =>expert needed
I have ordered one waveshare boards based on the same devices: will try as soon as I have received samples. Thanks to point this feature!
Great, I recommend they are so cheap and so fast.
Supported should be esp32 S2, S3, C3, C6 and maybe few others. "Magic" iomux values that route jtag to external pins for s3 are undocumented but on the forums obviously I found required info :)
On Wed, Jan 1, 2025 at 6:30 PM Gwenhael Goavec-Merou < @.***> wrote:
I have ordered one waveshare boards based on the same devices: will try as soon as I have received samples. Thanks to point this feature!
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I have received my board, I suppose firmware is correctly flashed. I observe issues for read command. Could you provides a dump to compare?
hardware runs this JTAG so firmware is here only to initialize registers, assigns signals to pins and wait.
openocd was only that worked (after I fixed) I haven't tried any longer reads but now I can pull your source and check if I can see something strendge
On Sun, Jan 12, 2025 at 9:07 AM Gwenhael Goavec-Merou < @.***> wrote:
I have received my board, I suppose firmware is correctly flashed. I observe issues for read command. Could you provides a dump to compare?
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Here is compiled dump of my firmware small 14-pin S3 board pinout is on my git https://github.com/emard/esp32s3-jtag
On Sun, Jan 12, 2025 at 11:28 AM D EMARD @.***> wrote:
hardware runs this JTAG so firmware is here only to initialize registers, assigns signals to pins and wait.
openocd was only that worked (after I fixed) I haven't tried any longer reads but now I can pull your source and check if I can see something strendge
On Sun, Jan 12, 2025 at 9:07 AM Gwenhael Goavec-Merou < @.***> wrote:
I have received my board, I suppose firmware is correctly flashed. I observe issues for read command. Could you provides a dump to compare?
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I have also some old devkit-1 ESP32S3 board
https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/user_guide_v1.0.html
If you have this board and can't get it working I can compile and see what happens
On Sun, Jan 12, 2025 at 11:37 AM D EMARD @.***> wrote:
Here is compiled dump of my firmware small 14-pin S3 board pinout is on my git https://github.com/emard/esp32s3-jtag
On Sun, Jan 12, 2025 at 11:28 AM D EMARD @.***> wrote:
hardware runs this JTAG so firmware is here only to initialize registers, assigns signals to pins and wait.
openocd was only that worked (after I fixed) I haven't tried any longer reads but now I can pull your source and check if I can see something strendge
On Sun, Jan 12, 2025 at 9:07 AM Gwenhael Goavec-Merou < @.***> wrote:
I have received my board, I suppose firmware is correctly flashed. I observe issues for read command. Could you provides a dump to compare?
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Sorry for the delay to answer: no needs to prepare code/firmware. I'm now able to read IDCODE \o/.
I have to cleanup my local directly before pushing modifications in your branch. After that I see some improvements.
Thanks!
eheheeee wonderful!
One notice while I was experimienting with driver in openocd, this usb-jtag works good only if repeated commands are repeated using its special usb command for repeating
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
here is this function used for repeating see function esp_usb_jtag_write_rlestream()
https://github.com/espressif/openocd-esp32/blob/6bcb287a9deec4f9f68f6a8939b60792f55e9927/src/jtag/drivers/esp_usb_jtag.c#L482
I if replace it this CMD_REP command with simple for-loop that repeats "cmd" command "ct" number of times, then something doesn't work and usb timeout error appears.
On Tue, Jan 14, 2025 at 7:50 AM Gwenhael Goavec-Merou < @.***> wrote:
Sorry for the delay to answer: no needs to prepare code/firmware. I'm now able to read IDCODE \o/.
I have to cleanup my local directly before pushing modifications in your branch. After that I see some improvements.
Thanks!
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Very curious about any updates around this. Currently designing a board that uses the ESP32-S3-Mini-1 and a Tang Mega 60 and would love to be able to use the code from esp-usb-bridge along with openfpgaloader to program the FPGA.
Last time I remember it returns correct fpga chip id but bitstream programming stops with some usb errors So the basic mechanism is working but needs a bit more fiddling to work. there is openocd code which works with S3. Also you can check my https://github.com/emard/esp32ecp5 it works on S3 same as on classic ESP32. S3 USB can additional run https://github.com/emard/esp32ecp5/blob/master/dfu.py so with any DFU client you can program FPGA and FLASH very fast using USB
On Fri, Mar 21, 2025 at 5:48 AM Ed Anuff @.***> wrote:
Very curious about any updates around this. Currently designing a board that uses the ESP32-S3-Mini-1 and a Tang Mega 60 and would love to be able to use the code from esp-usb-bridge https://github.com/espressif/esp-usb-bridge along with openfpgaloader to program the FPGA.
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Very curious about any updates around this. Currently designing a board that uses the ESP32-S3-Mini-1 and a Tang Mega 60 and would love to be able to use the code from esp-usb-bridge https://github.com/espressif/esp-usb-bridge along with openfpgaloader to program the FPGA.
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Ups only detail esp32ecp5 supports ecp5 artix7 cycloe5 no gw yet. openocd could work if board has jtag and bitstream can be converted so .svf file
you can patch and compile openocd https://github.com/emard/esp32s3-jtag/blob/main/openocd/espfix.patch I did it on linux its easy
@edanuff I confirm: basics functions are working (FPGA detect and idCode) but writing a full bitstream is not working. I try to find with small tests the cause of this failure. But not observed issue with USB.
@edanuff @emard with latest commit I'm able to load a bitstream with ECP5 based board. Latest issue was related to the last TDI bit sent with tms transaction (SHIFTIR/SHIFTDR -> EXIT1IR/EXIT1DR). I have now to test if it's working with SPI Flash, check for TDO and FLUSH command before merging this support. Could you test in your side to confirm/infirm my results? Thanks.
@edanuff @emard with latest commit I'm able to load a bitstream with ECP5 based board.
Is that the esp_usb_jtag branch? I'll give it a shot
It works for ECP5 25F, and it is very fast!
esp32s3 xiao mini is connected to jtag of ulx3s ecp5 25f with arduino i compiled and uploaded https://github.com/emard/esp32s3-jtag to S3 I pulled openFPGALoader branch esp_usb_jtag, compiled
time /tmp/openFPGALoader/build/openFPGALoader -c esp32s3 ulx3s_25f_oscg_blink.bit empty 0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0 esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255 Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6 Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [==================================================] 100.00% Done Disable configuration: DONE drain_in
real 0m2,982s user 0m0,008s sys 0m0,124s
On Sun, Mar 23, 2025 at 11:49 PM Gwenhael Goavec-Merou @.***> wrote:
@edanuff @emard with latest commit I'm able to load a bitstream with ECP5 based board. Latest issue was related to the last TDI bit sent with tms transaction (SHIFTIR/SHIFTDR -> EXIT1IR/EXIT1DR). I have now to test if it's working with SPI Flash, check for TDO and FLUSH command before merging this support. Could you test in your side to confirm/infirm my results? Thanks.
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trabucayre left a comment (trabucayre/openFPGALoader#501)
@edanuff @emard with latest commit I'm able to load a bitstream with ECP5 based board. Latest issue was related to the last TDI bit sent with tms transaction (SHIFTIR/SHIFTDR -> EXIT1IR/EXIT1DR). I have now to test if it's working with SPI Flash, check for TDO and FLUSH command before merging this support. Could you test in your side to confirm/infirm my results? Thanks.
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I'm getting the following:
% ./openFPGALoader --scan-usb
empty
Bus device vid:pid probe type manufacturer serial product
% ./openFPGALoader -c esp32s3 --detect
empty
fails to open esp_usb_jtag device vid:pid 0x303a:0x
JTAG init failed with: std::exception
however, if I change the pid to 1002 in cable.hpp to match the Espressif USB JTAG bridge, I get this:
% ./openFPGALoader --scan-usb
empty
Bus device vid:pid probe type manufacturer serial product
005 002 0x303a:0x1002 esp32s3 Espressif Systems Co. Ltd. 64E8335D11A0 ESP USB Bridge
% ./openFPGALoader -c esp32s3 --detect
empty
fails to open esp_usb_jtag device vid:pid 0x303a:0x
JTAG init failed with: std::exception
% ./openFPGALoader -c esp32s3 ../pmod_led.fs
empty
fails to open esp_usb_jtag device vid:pid 0x303a:0x
JTAG init failed with: std::exception
Not sure is the is due to differences between @emard's bridge versus the Espressif code on the ESP32?
@emard thanks! Yes I have observed the load is fast.
@edanuff Have you updated your esp32 with https://github.com/emard/esp32s3-jtag ? Could you also try with sudo to check if the issue is related to access right.
I have tested with esp-usb-bridge. I wish to finalize first with @emard's firmware before trying to see if both are compatibles and adapt the code accordingly.
@trabucayre I don't actually see the firmware in https://github.com/emard/esp32s3-jtag. Is it the esp32s3-jtag.ino file? If so, I wasn't able to get that to build.
.ino is the C source not binary atart arduino ide and load this .ino some editor window will open this file.
follow hints in .ino file comments to select your board e.g. if it is XIAO MINI ESP32S3
Tools->Board->Boards Manager->esp32 by espressif Tools->USB CDC On Boot: Enabled Tools->CPU Frequency: 80 MHz (WiFi) Tools->Board: XIAO_ESP32S3 Tools->JTAG Adapter: Integrated USB JTAG Tools->USB Mode: Hardware CDC and JTAG
near top left corner of the window will be a circular blue "button" with right arrow (->), click this it will compile source and upload to your board
On Mon, Mar 24, 2025 at 8:01 AM Ed Anuff @.***> wrote:
@trabucayre https://github.com/trabucayre I don't actually see the firmware in https://github.com/emard/esp32s3-jtag. Is it the esp32s3-jtag.ino https://github.com/emard/esp32s3-jtag/blob/main/esp32s3-jtag.ino file? If so, I wasn't able to get that to build.
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@trabucayre https://github.com/trabucayre I don't actually see the firmware in https://github.com/emard/esp32s3-jtag. Is it the esp32s3-jtag.ino https://github.com/emard/esp32s3-jtag/blob/main/esp32s3-jtag.ino file? If so, I wasn't able to get that to build.
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@emard thanks, I was able to get it to program. I am using the ESP32-S3-DevKitM-1 board with this, however I do need to set the board as XIAO_ESP32S3 for it to compile in the Arduino IDE. Otherwise, I get "error: no matching function for call to 'HardwareSerial::begin()'". I'm not seeing anything significantly different between the two board types so it shoudl be okl to just keep the XIAO_ESP32S3 board type with this.
Once I do this, I get:
% ./openFPGALoader --scan-usb
empty
Bus device vid:pid probe type manufacturer serial product
005 001 0x303a:0x1001 esp32s3 Espressif 64:E8:33:5D:11:A0 USB JTAG/serial debug unit
% ./openFPGALoader -c esp32s3 --detect
empty
0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0
esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255
Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6
index 0:
idcode 0x9604093
manufacturer xilinx
family xc9500xl
model xc9572xl
irlength 8
drain_in
% ./openFPGALoader -c esp32s3 ../../../GitHub/a2bridge/a2bridge.jed
empty
0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0
esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255
Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6
Open file DONE
Erase flash zsh: segmentation fault ./openFPGALoader -c esp32s3 ../../../GitHub/a2bridge/a2bridge.jed
and trying with a different device (Tang Mega 60K), I get:
% ./openFPGALoader -c esp32s3 --detect
empty
0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0
esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255
Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6
JTAG init failed with: Unknown device with IDCODE: 0x0001481b (manufacturer: 0x40d (Gowin), part: 0x00 vers: 0x0
which is probably to be expected since openfpgaloader doesn't support Gowin GW5AT-60 parts yet, only GW5AT-138.
One more try with a supported chip (Tang Primer 20K):
% ./openFPGALoader -c esp32s3 --detect
empty
0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0
esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255
Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6
index 0:
idcode 0x81b
manufacturer Gowin
family GW2A
model GW2A(R)-18(C)
irlength 8
drain_in
% ./openFPGALoader -c esp32s3 ../uart_Hello.fs
empty
0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0
esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255
Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6
Parse file Parse ../uart_Hello.fs:
Done
DONE
Load SRAM: [==================================================] 100.00%
Done
DONE
xfer: usb bulk write failed with error -7
ESP USB Jtag drain_in failed
here is now binary release of esp32s3-jtag firmware https://github.com/emard/esp32s3-jtag/tree/main/binary
For such simple source all boards are the same, some have onboard LED, SERIAL some don't, it doesn't matter for JTAG, it's good enough to have compiled binary for any ESP32S3 board.
Looking at issues, I think Gwen would have few small bugs to fix in order to support different chips than ECP5 :) but I think we are close to getting it fully working.
On Mon, Mar 24, 2025 at 8:05 PM Ed Anuff @.***> wrote:
One more try with a supported chip (Tang Primer 20K):
% ./openFPGALoader -c esp32s3 --detect empty 0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0 esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255 Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6 index 0: idcode 0x81b manufacturer Gowin family GW2A model GW2A(R)-18(C) irlength 8 drain_in % ./openFPGALoader -c esp32s3 ../uart_Hello.fs empty 0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0 esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255 Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6 Parse file Parse ../uart_Hello.fs: Done DONE Load SRAM: [==================================================] 100.00% Done DONE xfer: usb bulk write failed with error -7 ESP USB Jtag drain_in failed
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One more try with a supported chip (Tang Primer 20K):
% ./openFPGALoader -c esp32s3 --detect empty 0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0 esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255 Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6 index 0: idcode 0x81b manufacturer Gowin family GW2A model GW2A(R)-18(C) irlength 8 drain_in % ./openFPGALoader -c esp32s3 ../uart_Hello.fs empty 0x1 0xa 0x1 0x8 0x40 0x1f 0x1 0x0 0xff 0x0 esp_usb_jtag: Device found. Base speed 40000 KHz, div range 1 to 255 Jtag frequency : requested 6000000Hz -> real 6000000Hz divisor=6 Parse file Parse ../uart_Hello.fs: Done DONE Load SRAM: [==================================================] 100.00% Done DONE xfer: usb bulk write failed with error -7 ESP USB Jtag drain_in failed
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Hi and thanks for these tests. Gowin 60K is supported but in master branch: I have to rebase, squash commits. I have to also check or removes drain_in: seems not required. My idea is in first time to verify everything with ECP5 before starting to test with another FPGA. For the 20k drain_in fails at destructor level: but I suppose the FPGAs is not working? @emard indeed there is small bugs to fix, maybe not visible with ECP5.
For Lattice ECP5 on ULX3S programming FPGA RAM and FLASH works faster than ever before :)
On Mon, Mar 24, 2025 at 9:13 PM Gwenhael Goavec-Merou < @.***> wrote:
Hi and thanks for these tests. Gowin 60K is supported but in master branch: I have to rebase, squash commits. I have to also check or removes drain_in: seems not required. My idea is in first time to verify everything with ECP5 before starting to test with another FPGA. For the 20k drain_in fails at destructor level: but I suppose the FPGAs is not working? @emard https://github.com/emard indeed there is small bugs to fix, maybe not visible with ECP5.
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Hi and thanks for these tests. Gowin 60K is supported but in master branch: I have to rebase, squash commits. I have to also check or removes drain_in: seems not required. My idea is in first time to verify everything with ECP5 before starting to test with another FPGA. For the 20k drain_in fails at destructor level: but I suppose the FPGAs is not working? @emard https://github.com/emard indeed there is small bugs to fix, maybe not visible with ECP5.
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@emard Great! Maybe I have to move to another device to check why it fails.
Yes try different boards, for ECP5 on ULX3S everything works great.
On Mon, Mar 24, 2025 at 9:43 PM Gwenhael Goavec-Merou < @.***> wrote:
@emard https://github.com/emard Great! Maybe I have to move to another device to check why it fails.
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@emard https://github.com/emard Great! Maybe I have to move to another device to check why it fails.
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@edanuff I have tested the esp32s3 with an board based on spartan6: I observe the same error with drain_in but I'm able to load and/or flash the bitstream successfully
With https://github.com/trabucayre/openFPGALoader/commit/c71668a1a2fc11db60ae0554f7f5c88d85a6e734 the error is discarded when drain_in is used to flush ESP32 device (error code mean timeout)
I have now to find my coolrunner CPLD ;-)