trabucayre
TE0711 S25FL256S QSPI Flash Error: Jedec ID : ff
Try to flash the TE0711 Model, which is Using Xilinx Arty xc7a100tcsg324 chip, with S25FL256S QSPI chip. Checked the constrain files, they are using same as the /usr/local/share/openFPGALoader/spiOverJtag_xc7a100tcsg324.bit.gz files is using. But every time, when try to flash the QSPI, return errors: openFPGALoader dose support S25FL256S chip, but the Jedec ID is FF is something not pulling chip information? BTW, I am using Digilent HS2 programmer.
openFPGALoader --fpga-part xc7a100tcsg324 -c digilent_hs2 Generator_V1.runs/impl_1/Generator.bin -f
load program
Flash SRAM: [==================================================] 100.00%
Done
Detail:
Jedec ID : ff
memory type : ff
memory capacity : ff
EDID + CFD length : ff
EDID : ffff
CFD :
flash chip unknown: use basic protection detection
unlock blocks
Error: block protection is set
can't unlock without --unprotect-flash
It's weird. When 0xffff is seen this mean an issue with SPI flash communication (in fact it's bad to continue in this situation => I have to fix that).
Could you redo with -v to have more informations?
I have checked the schematic and the flash is connected with the same pinout.
Thanks
Thanks for the responds, please see attached output after put -v
~/Documents/Xilinx/Arty/GeneratorFPGA$ openFPGALoader --fpga-part xc7a100tcsg324 -c digilent_hs2 Generator_V1.runs/impl_1/Generator.bin -f -v
write to flash
Jtag frequency : requested 6.00MHz -> real 6.00MHz
found 1 devices
index 0:
idcode 0x3631093
manufacturer xilinx
family artix a7 100t
model xc7a100
irlength 6
File type : bin
Open file DONE
Parse file DONE
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7a100tcsg324.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
ff ff ff ff read ffffffff
Detail:
Jedec ID : ff
memory type : ff
memory capacity : ff
EDID + CFD length : ff
EDID : ffff
CFD : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
RDSR : fc
WIP : 0
WEL : 0
BP : f
TB : 1
SRWD : 1
flash chip unknown: use basic protection detection
unlock blocks
Error: block protection is set
can't unlock without --unprotect-flash
csn has the same role as address in i2c protocol: it is used to address one peripheral. If csn is high peripheral doesn't take into account data in si and sck. This why you have always '0'.
Quad enable is bit 1 from CR1 register to configure flash into quad mode: required when you build a bitstream with x4 data bus widths.
It's maybe because the device is in quad mode openFPGALoader is unable to communicate with him => I have to check that.
Could you please provides the full code of your device, others option is the bitstream for xc7a100ticsg324-1L is not compatible with XC7A100T-2CSG324C or XC7A100T-2CSG324I
I removed some of comments above, because I build my own spiOverJtag bit file using wrong FPGA family. My comment above is the from correct device family output.
The device is "xc7a100tcsg324-2". I could program Using Xilinx directly.
Regarding quad mode, the openFPGALoader get this information from _jedec_id, how could I know it communication have never been build? looks _jedec_id is FFFFFF, which means, chips never been selected.
jedec_id is read from register 0x90. Value read may be because csn never goes low, flash powered down or something wrong into FPGA. I have to read again the datasheet, to see for something like this.
If you want, I could team-viewer in my computer, you could remote work on the board if that is helpful for you.
trying to see if chip has been selected:
assign csn = fsm_csn;
assign LEDR = ~fsm_csn;
The LED Red flashing quick, looks it does turn low.
Ok so the bitstream is worling: good thing. For team-viewer thanks but my home internet connection it's not possible and it's more easy to have access to the hardware. first I have to check datasheet and to try with board with the same device to see why jedec read is not working.
that sounds good. BTW, if you are located at United States, I could send one board to you to test. But looks you are not.
Thanks but I live in France... Anyway first I have to try with hardware I have :)
Quick update, just tried to program the TE0711(same SOM) with TE0703 carrier board https://wiki.trenz-electronic.de/display/PD/TE0703+TRM , instead of utilizing Digilent's programer, I could successfully program the Flash without any issue.
Our system is using Jtag : Digilent_hs2 https://www.digikey.com/en/products/detail/digilent-inc/410-249/3902812, TE0703 on board Jtag is Digilent, don't know that will lead the different or not.
~/Documents/Xilinx/Arty/GeneratorFPGA$ openFPGALoader --fpga-part xc7a100tcsg324 -c digilent Generator_V1.runs/impl_1/Generator.bin -f -v
write to flash
Jtag frequency : requested 6.00MHz -> real 6.00MHz
found 1 devices
index 0:
idcode 0x3631093
manufacturer xilinx
family artix a7 100t
model xc7a100
irlength 6
File type : bin
Open file DONE
Parse file DONE
use: /usr/local/share/openFPGALoader/spiOverJtag_xc7a100tcsg324.bit.gz
load program
Flash SRAM: [==================================================] 100.00%
Done
1 2 19 4d read 102194d
Detected: spansion S25FL256S 512 sectors size: 256Mb
RDSR : 00
WIP : 0
WEL : 0
BP : ca
TB : 224
SRWD : 0
00000000 00000000 00000000 00
Erasing: [==================================================] 100.00%
Done
Writing: [==================================================] 100.00%
Done
parallels@vm:~/Documents/Xilinx/Arty/GeneratorFPGA$
It's partially a good news: this mean spi flash is working, and openFPGALoader has no difficulties to communicate! (Could you retry with official spiOverJtag for this device to check if it compatible?).
But it's weird: I checked TE0711 schematic and I have not seen anything explaining why with this carrier it's works and with your setup no... Have you tried to load bitstream in SRAM? digilent_hs2 is fully supported (it's one of probe I use the most) it's based on FT232H, digilent on FT2232H, and since your able in your setup to get FPGA idcode it's mean hs2 is working...
After a long day try, I think I found the reason why system persist me flash the QSPI flash. Last night try was success because I used a new FPGA SOM and flash the new code (not the code I used at office). This morning, I tried again to flash the same hardware use office's code, which give me same FFFFFF output again. So, not as I thought it was the Digilent programer issue.
I dig into the constrain code, find this line in my office project
set_property BITSTREAM.CONFIG.PERSIST YES [current_design]
This prevent me programing using openFPGALoader, but Xilinx Programer could works fine.
This is under the Vivado>Synthesis Tab>Edit Device Properties>Configuration>Prohibit usage of configuration pins as user I/O and persist after configuration should be NO.
After changed to No or delete the constrain code line, I tested the code utilizing your latest code directly without any issue.
Again, I appreciate for you help in last two days and try out back and forth with my misleading information. I hope other people who comes into same situation could saw this thread and find the solution.
Thank you! Best Regards
Thanks for your feedback: this information must be added to Troubleshooting page and/or xilinx page. I have to check howto fix that -> if xilinx programmer is able to deal with this situation I have to add the correct configuration to do the same with openFPGALoader. Thanks again
Glad could contribute little bit. It is very interesting to know how Xilinx JTAG could flash QSPI event if it pin maintains the configuration logic access BITSTREAM.CONFIG. PERSIST YES.
Last night tried to recompile the spiOverJtag by adding constrain file BITSTREAM.CONFIG. PERSIST NO see it this RAM bit file could unlock the QSPI persist configuration pin, but without success.
UG908 did not give more detail about how Xilinx JTAG server tell FPGA to flash and pull down the csn pin after pin been persisted.
Just an idea about how could bypass it. Is the STARTUPE3 primitive could help to prevent those i/o been persisted? https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf page 115 is showing the STARTUPE3 is have DI/DO/DTS and FCSBO, which will not like spiOverJtag control the SPI over I/O pin.
STARTUPE3 primitive is for ultrascale FPGA and not for serie7.
I have to find document about persist to see how to reset pins configuration.