up5k differential pairs

[peepo]

Hi Tom, on this page https://tomverbeure.github.io/2022/12/27/The-ICE-V-Wireless-FPGA-Board.html you mention differential pairs. [1]

Had you any experience using? in particular: is any special code needed to instantiate? ie like LVDS on other ice40 products.

thanks

"the PCB silk screen shows the FPGA pin number of each PMOD IO pin, as well as the polarity of differential FPGA IO pairs."

[tomverbeure]

Hi!

No, I've never used them.

I don't think there's a way in which Yosys will infer these kind of IOs. The way to go is to manually instantiate them in the RTL. I do this here for DDR IOs. The process for LVDS IOs should similar: https://github.com/mystorm-org/BlackIce-II/blob/77474a3cd72b149cc86b580e151d85ec93c7e440/examples/sram/src/sram_io_ice40.v#L124-L139

Check out section 10.3 of this Lattice document. https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/UZ/FPGA-TN-02213-1-7-Using-Differential-IO-LVDS-Sub-LVDS-iCE40-LP-HX.ashx?document_id=47960

Tom