Silice
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sylefeb
Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.
Due to the way Verilog inputs/outputs are written by Silice, and limitations of the import, Silice cannot directly re-import the modules it exports.
Hi to all Any one here has experience with Altera Cyclone IV EP4CE6E22C8N? How can I check my project resource consumption on for EP4CE6E22C8N? Thanks
A versioning approach needs to be defined: - tags on `master` branch on new versions (when merging from `wip`), where the tag is an actual version string (good practices?) -...
Hello Sylvain, I am trying to set the subroutine permission to access "a1.value" in the algorithm "a" without success. ``` algorithm a(input uint1 value) { uint1 local_value = uninitialized; while...
I'll start the first one: In my attempt to debug WaitForRisingEdge by passing in a debug LED I now receive the following error message: ``` ^^^^^^^^^^^^^^^^^^^ incorrect input parameters in...
Following discussion in #219 there is a cleaner way to write the compilation scripts (calls to gcc, the `compile_c.sh` bash scripts in project files). Scripts could use an update overall.
Trackers defined in pipeline stages are not properly tagging trickling variable usage. The trickling vios used in the tracker are not seen as used and end up being optimized out....
There are several limitations when binding to outputs: - ~~Partial bindings (with bit/part select) is unsupported, an error is correctly reported~~ a first prototype is in draft, requires testing and...
Extra pins would be tagged onto the input/output. This would give extra flexibility when a specific feature is not exposed in the framework, or when the pins are used in...
Given this circuit: `circuitry copycoordinates( input x, input y, output x1, output y1 ) { x1 = x; y1 = y; } ` Using outputs from an algorithm as inputs...
