surf

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Fix linkedGet and linkedSet calls in Rogue Devices

1

### Description Update Rogue code to reflect best practices for LinkedVariables. ### Details

bengineerd

### Description - #1158 - #1159 - #1161

ruck314

### Description - #1181 - #1180 - #1176

ruck314

### Description - adding warning message when Dirty Githash is detected

ruck314

Create ADS1217 ADC

3

### Description Created ADS1217 ADC VHDL module and with matching Python class. ### Details Created a new `AxiAds1217Core` VHDL module with AXI4-Lite register access to ADC data for all channels....

hsandber

Clean up of ethernet before adding RoCEv2.TX support

1

### Description - [depreciating VLAN support in ethernet/EthMacCore because never tested and never used](https://github.com/slaclab/surf/commit/9c6aee9d9c0a240ffdc0726d7dc13350faafbb8a)+ - [depreciating VLAN support in ethernet/IpV4Engine because never tested and never used](https://github.com/slaclab/surf/commit/7395517e522e4dcce39a696cf7981e9ece423e77)

ruck314

### Description There are many small changes, mostly to fix issues found in simulation. ### Details - AxiStreamResize - Better error reporting if generic assert fails - Ad9249ReadoutGroup2 - Initialize...

bengineerd

### Description ### Details ### JIRA ### Related

bengineerd

Multiple entries ARP table

5

Adding ARP table with multiple entries **PULL REQUEST IS STILL A DRAFT!** - Seems to work but more testing is needed ### Description - The file [ethernet/UdpEngine/rtl/ArpIpTable.vhd](https://github.com/FilMarini/surf/blob/multi-arp/ethernet/UdpEngine/rtl/ArpIpTable.vhd) contains a dynamic...

FilMarini

Check code quality in a continuous way

6

Hi, I analyzed the VHDL code from your surf project with Linty: https://oss.linty-services.com/dashboard?id=surf&codeScope=overall Do not get scared by the number of issues :-) It's just to provide you with data...

racodond