Variable Clock Speed for Verilog and Silice

[tcalospora]

It would be helpful if the max clock speed could be higher than around 4 mhz (and 25 mhz for VGA mode). I understand that the frequency is related to the display resolution and framerate and so can only be changed in specific ways. Wouldn't it be possible to double, triple, or quadruple the frequency, and then use a frequency divider to output pixel data at the same rate?

One cycle per pixel makes it extremely difficult to perform any math calculations on pixels and only allows the hardware to do blits or race the beam.

[sehugg]

In the VGA platform, you could implement your own clock divider and output duplicate pixels (and/or duplicate scanlines via line buffer) to create the illusion of multiple clock cycles per pixel. (Maybe this is more awkward in Silice though?)

But if you want a specific screen size/clock speed, you could change a line in this file:

this.setVideoParams(800-64, 520, 25000000);

It might be nice to have this be configurable as a Verilog define or something.