chisel-book

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Writing should have priority over reading

1

Suppose there is only one element in the FIFO (depth is 2), both read and write happens, the emptyReg should be false after this cycle

Phantom1003

There is something not clear in your good examples https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/Flasher.scala#L65-L74 https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/Flasher.scala#L126-L127 https://github.com/schoeberl/chisel-book/blob/master/src/main/scala/Flasher.scala#L134-L143 In the above examples, a hardware objects(timerReg, cntReg) are updated by multiple(two) conditionals It is confusing for beginners...

Hyunok-Kim

What do we do if we still want partial bulk connection

3

For 4.3 Bulk Connections, the ` If a name is missing, it is not connected.` seems to be deactivated already. What do we do if we still want to use...

HaFred

Possible bug in MemFifo in fifo.scala

2

HI, I believe there is a bug in the MemFifo implementation in fifo.scala. It is shown the figure below. If the FIFO gets two consecutive words (while empty) during which...

mmoghad

Build mobi version for Kindle

1

Is it possible to add to the build process the generation of a .mobi file for Kindle?

carlosedp

The multi-clock memory gives a warning with Chisel 5.0.2: ``` [deprecated] @[src/main/scala/MultiClockMemory.scala 26:21] (3 calls): The clock used to initialize the memory is different than the one used to initialize...

schoeberl

Fixes #43

pdnm

Hi @schoeberl, In `arbitrateSimp`, `regEmpty` is updated to true [when (out.ready)](https://github.com/schoeberl/chisel-book/blob/6f8bdcae7e5dd905e9e6c529344717c4f3eec860/src/main/scala/ArbiterTree.scala#L100), but what if `out.ready` is true when `regEmpty` is true? The following test fails while I think it should...

pdnm