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rust-embedded
Duplicated identifiers generated
The SVD file below generates two definitions of the struct PIO0_. This seems like a tricky edge case where the repetition is 0-3 + 6-32 with the same type, and exceptions for repetitions 4 and 5. The types for 0-3 and 6-32 are the same, so we should be able to reuse that?
Also I'm baffled by the generated code, why the first definition generates an array, and others an entry for each repetition? Specifically why the code generated by the first and fourth register definition differs, since the definition seems to be exactly the same except offsets and repetition numbers.
I think the correct behaviour would be to generate different entries for each element.
Click to expand!
pub pio0__: [PIO0__; 4], // Generated by the first register definition with repetition
#[doc = "0x10 - I/O configuration for open-drain pin PIO0_4"]
pub pio0_4: PIO0_4, // Generated by the second register definition without repetition
#[doc = "0x14 - I/O configuration for open-drain pin PIO0_5"]
pub pio0_5: PIO0_5, // Generated by the second register definition without repetition
#[doc = "0x18 - I/O configuration for port PIO0"]
pub pio0_6: PIO0_, // Generated by the fourth register definition with repetition
#[doc = "0x1c - I/O configuration for port PIO0"]
pub pio0_7: PIO0_, // Generated by the fourth register definition with repetition
#[doc = "0x20 - I/O configuration for port PIO0"]
pub pio0_8: PIO0_, // Generated by the fourth register definition with repetition
#[doc = "0x24 - I/O configuration for port PIO0"]
pub pio0_9: PIO0_, // Generated by the fourth register definition with repetition
<peripheral>
<name>IOCON</name>
<description>I/O control (IOCON) </description>
<groupName>IOCON</groupName>
<baseAddress>0x40044000</baseAddress>
<addressBlock>
<offset>0x0</offset>
<size>0xFFF</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<dim>4</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-3</dimIndex>
<name>PIO0_%s</name>
<description>I/O configuration for port PIO0</description>
<addressOffset>0x000</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_4</name>
<description>I/O configuration for open-drain pin PIO0_4</description>
<addressOffset>0x010</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function. </description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>I2CMODE</name>
<description>Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE_FAST</name>
<description>Standard mode/ Fast-mode I2C.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STANDARD_IO_FUNCTIO</name>
<description>Standard I/O functionality</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE_PLUS_I2C</name>
<description>Fast-mode Plus I2C</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<name>PIO0_5</name>
<description>I/O configuration for open-drain pin PIO0_5</description>
<addressOffset>0x014</addressOffset>
<access>read-write</access>
<resetValue>0x00000080</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function. </description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[7:3]</bitRange>
</field>
<field>
<name>I2CMODE</name>
<description>Selects I2C mode (see Section 7.3.8). Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000).</description>
<bitRange>[9:8]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>STANDARD_MODE_FAST</name>
<description>Standard mode/ Fast-mode I2C.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>STANDARD_IO_FUNCTIO</name>
<description>Standard I/O functionality</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>FAST_MODE_PLUS_I2C</name>
<description>Fast-mode Plus I2C</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>RESERVED</name>
<description>Reserved.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:10]</bitRange>
</field>
</fields>
</register>
<register>
<dim>18</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>6-23</dimIndex>
<name>PIO0_%s</name>
<description>I/O configuration for port PIO0</description>
<addressOffset>0x018</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>32</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-31</dimIndex>
<name>PIO1_%s</name>
<description>I/O configuration for port PIO1</description>
<addressOffset>0x060</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>2</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0-1</dimIndex>
<name>PIO2_%s</name>
<description>I/O configuration for port PIO2</description>
<addressOffset>0x0F0</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
<register>
<dim>22</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>2-23</dimIndex>
<name>PIO2_%s</name>
<description>I/O configuration for port PIO2</description>
<addressOffset>0x0FC</addressOffset>
<access>read-write</access>
<resetValue>0x00000090</resetValue>
<resetMask>0xFFFFFFFF</resetMask>
<fields>
<field>
<name>FUNC</name>
<description>Selects pin function.</description>
<bitRange>[2:0]</bitRange>
</field>
<field>
<name>MODE</name>
<description>Selects function mode (on-chip pull-up/pull-down resistor control).</description>
<bitRange>[4:3]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INACTIVE_NO_PULL_DO</name>
<description>Inactive (no pull-down/pull-up resistor enabled).</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_DOWN_RESISTOR_E</name>
<description>Pull-down resistor enabled.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>PULL_UP_RESISTOR_ENA</name>
<description>Pull-up resistor enabled.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>REPEATER_MODE</name>
<description>Repeater mode.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>HYS</name>
<description>Hysteresis.</description>
<bitRange>[5:5]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLE</name>
<description>Enable.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>INV</name>
<description>Invert input</description>
<bitRange>[6:6]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>INPUT_NOT_INVERTED</name>
<description>Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0).</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>INPUT_INVERTED_HIGH</name>
<description>Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1).</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[9:7]</bitRange>
</field>
<field>
<name>OD</name>
<description>Open-drain mode.</description>
<bitRange>[10:10]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>DISABLE</name>
<description>Disable.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>ENABLED</name>
<description>Enabled. Open-drain mode enabled. This is not a true open-drain mode.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>S_MODE</name>
<description>Digital filter sample mode.</description>
<bitRange>[12:11]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>BYPASS_INPUT_FILTER</name>
<description>Bypass input filter.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>1_CLOCK_CYCLE</name>
<description>1 clock cycle. Input pulses shorter than one filter clock are rejected.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>2_CLOCK_CYCLES</name>
<description>2 clock cycles. Input pulses shorter than two filter clocks are rejected.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>3_CLOCK_CYCLES</name>
<description>3 clock cycles. Input pulses shorter than three filter clocks are rejected.</description>
<value>0x3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CLKDIV</name>
<description>Select peripheral clock divider for input filter sampling clock IOCONCLKDIV. Value 0x7 is reserved.</description>
<bitRange>[15:13]</bitRange>
<enumeratedValues>
<name>ENUM</name>
<enumeratedValue>
<name>IOCONCLKDIV0</name>
<description>IOCONCLKDIV0. Use IOCON clock divider 0.</description>
<value>0x0</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV1</name>
<description>IOCONCLKDIV1. Use IOCON clock divider 1.</description>
<value>0x1</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV2</name>
<description>IOCONCLKDIV2 Use IOCON clock divider 2.</description>
<value>0x2</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV3</name>
<description>IOCONCLKDIV3. Use IOCON clock divider 3.</description>
<value>0x3</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV4</name>
<description>IOCONCLKDIV4. Use IOCON clock divider 4.</description>
<value>0x4</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV5</name>
<description>IOCONCLKDIV5. Use IOCON clock divider 5.</description>
<value>0x5</value>
</enumeratedValue>
<enumeratedValue>
<name>IOCONCLKDIV6</name>
<description>IOCONCLKDIV6. Use IOCON clock divider 6.</description>
<value>0x6</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RESERVED</name>
<description>Reserved.</description>
<bitRange>[31:16]</bitRange>
</field>
</fields>
</register>
</registers>
Github have gist: https://gist.github.com/
svd2rust creates array only if first item has index 0.
Ah gotcha, that makes sense, although it is weird in this case. Is there a way to make it not generate an array?
Also this is an inconvenience, and odd, but the real problem is the duplicated identifier being generated.
Is there a way to make it not generate an array
We can add this as option.
But in your case PIO0_4 and PIO0_5 differ from others so all works as expected.
The problem is that PIO0-3 and PIO6-31 have the same type, and because of this the PIO_ struct is generated twice (although identically), and the crate fails to build. Also PIO0-3 is an array, while PIO6-31 is generated separately, and PIO4,5 have different types.
I see only one way: rename PIO_%s 6-31. Then they will have other type.
As option you can <deriveFrom> this from first part to use same type, but I think this don't work with arrays yet (need to check).
Yeah that's the workaround for now, but that makes accessing those registers even more inconsistent. rust2svd should either understand that the two definitions for PIO%s are identical, and not generate the structs twice, or the dimIndex should accept non-continous blocks, but I guess that's not part of the SVD specification, so that's a no go.
This is exactly what I set out to do in my PR. I bootleged your <peripheral> snippet into an SVD to run it through svd2rust with the changes in #662. Now svd2rust generates the following RegisterBlock:
Click to expand
#[doc = r"Register block"]
#[repr(C)]
pub struct RegisterBlock {
#[doc = "0x00..0x10 - I/O configuration for port PIO0"]
pub pio0_: [PIO0_; 4],
#[doc = "0x10 - I/O configuration for open-drain pin PIO0_4"]
pub pio0_4: PIO0_4,
#[doc = "0x14 - I/O configuration for open-drain pin PIO0_5"]
pub pio0_5: PIO0_5,
#[doc = "0x18 - I/O configuration for port PIO0"]
pub pio0_6: PIO0_6,
#[doc = "0x1c - I/O configuration for port PIO0"]
pub pio0_7: PIO0_6,
#[doc = "0x20 - I/O configuration for port PIO0"]
pub pio0_8: PIO0_6,
#[doc = "0x24 - I/O configuration for port PIO0"]
pub pio0_9: PIO0_6,
#[doc = "0x28 - I/O configuration for port PIO0"]
pub pio0_10: PIO0_6,
#[doc = "0x2c - I/O configuration for port PIO0"]
pub pio0_11: PIO0_6,
#[doc = "0x30 - I/O configuration for port PIO0"]
pub pio0_12: PIO0_6,
#[doc = "0x34 - I/O configuration for port PIO0"]
pub pio0_13: PIO0_6,
#[doc = "0x38 - I/O configuration for port PIO0"]
pub pio0_14: PIO0_6,
#[doc = "0x3c - I/O configuration for port PIO0"]
pub pio0_15: PIO0_6,
#[doc = "0x40 - I/O configuration for port PIO0"]
pub pio0_16: PIO0_6,
#[doc = "0x44 - I/O configuration for port PIO0"]
pub pio0_17: PIO0_6,
#[doc = "0x48 - I/O configuration for port PIO0"]
pub pio0_18: PIO0_6,
#[doc = "0x4c - I/O configuration for port PIO0"]
pub pio0_19: PIO0_6,
#[doc = "0x50 - I/O configuration for port PIO0"]
pub pio0_20: PIO0_6,
#[doc = "0x54 - I/O configuration for port PIO0"]
pub pio0_21: PIO0_6,
#[doc = "0x58 - I/O configuration for port PIO0"]
pub pio0_22: PIO0_6,
#[doc = "0x5c - I/O configuration for port PIO0"]
pub pio0_23: PIO0_6,
#[doc = "0x60..0xe0 - I/O configuration for port PIO1"]
pub pio1_: [PIO1_; 32],
_reserved22: [u8; 0x10],
#[doc = "0xf0..0xf8 - I/O configuration for port PIO2"]
pub pio2_: [PIO2_; 2],
_reserved23: [u8; 0x04],
#[doc = "0xfc - I/O configuration for port PIO2"]
pub pio2_2: PIO2_2,
#[doc = "0x100 - I/O configuration for port PIO2"]
pub pio2_3: PIO2_2,
#[doc = "0x104 - I/O configuration for port PIO2"]
pub pio2_4: PIO2_2,
#[doc = "0x108 - I/O configuration for port PIO2"]
pub pio2_5: PIO2_2,
#[doc = "0x10c - I/O configuration for port PIO2"]
pub pio2_6: PIO2_2,
#[doc = "0x110 - I/O configuration for port PIO2"]
pub pio2_7: PIO2_2,
#[doc = "0x114 - I/O configuration for port PIO2"]
pub pio2_8: PIO2_2,
#[doc = "0x118 - I/O configuration for port PIO2"]
pub pio2_9: PIO2_2,
#[doc = "0x11c - I/O configuration for port PIO2"]
pub pio2_10: PIO2_2,
#[doc = "0x120 - I/O configuration for port PIO2"]
pub pio2_11: PIO2_2,
#[doc = "0x124 - I/O configuration for port PIO2"]
pub pio2_12: PIO2_2,
#[doc = "0x128 - I/O configuration for port PIO2"]
pub pio2_13: PIO2_2,
#[doc = "0x12c - I/O configuration for port PIO2"]
pub pio2_14: PIO2_2,
#[doc = "0x130 - I/O configuration for port PIO2"]
pub pio2_15: PIO2_2,
#[doc = "0x134 - I/O configuration for port PIO2"]
pub pio2_16: PIO2_2,
#[doc = "0x138 - I/O configuration for port PIO2"]
pub pio2_17: PIO2_2,
#[doc = "0x13c - I/O configuration for port PIO2"]
pub pio2_18: PIO2_2,
#[doc = "0x140 - I/O configuration for port PIO2"]
pub pio2_19: PIO2_2,
#[doc = "0x144 - I/O configuration for port PIO2"]
pub pio2_20: PIO2_2,
#[doc = "0x148 - I/O configuration for port PIO2"]
pub pio2_21: PIO2_2,
#[doc = "0x14c - I/O configuration for port PIO2"]
pub pio2_22: PIO2_2,
#[doc = "0x150 - I/O configuration for port PIO2"]
pub pio2_23: PIO2_2,
}
#[doc = "PIO0_ (rw) register accessor: an alias for `Reg<PIO0__SPEC>`"]
pub type PIO0_ = crate::Reg<pio0_::PIO0__SPEC>;
#[doc = "I/O configuration for port PIO0"]
pub mod pio0_;
pub use pio0_ as pio0_4;
pub use pio0_ as pio0_5;
pub use pio0_ as pio0_6;
pub use PIO0_ as PIO0_4;
pub use PIO0_ as PIO0_5;
pub use PIO0_ as PIO0_6;
#[doc = "PIO1_ (rw) register accessor: an alias for `Reg<PIO1__SPEC>`"]
pub type PIO1_ = crate::Reg<pio1_::PIO1__SPEC>;
#[doc = "I/O configuration for port PIO1"]
pub mod pio1_;
#[doc = "PIO2_ (rw) register accessor: an alias for `Reg<PIO2__SPEC>`"]
pub type PIO2_ = crate::Reg<pio2_::PIO2__SPEC>;
#[doc = "I/O configuration for port PIO2"]
pub mod pio2_;
pub use pio2_ as pio2_2;
pub use PIO2_ as PIO2_2;
Some of the names aren't as ergonomic as I'd like such as pio0_7 being of type PIO0_6, but this was the least complicated way to ensure:
- All types were accounted for
- There exist no naming collisions or duplicate re-exports (
pub use) - Any register that can be inferred to share the same type, will in fact share the same type even if it's done through a re-export
Actually your issue already points out some room for improvement in that not only must the register name regex match but the fields as well before determining that the types should be implicitly derived.
Actually your issue already points out some room for improvement in that not only must the register name regex match but the fields as well before determining that the types should be implicitly derived.
Exactly.