riscv
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rust-embedded
Low level access to RISC-V processors
Emit `cargo::rustc-check-cfg=CHECK_CFG` in build.rs so that they can be cross-checked even if cfg option itself isn't set.
Without needing to touch the CSR. This allows multiple changes in a single register write.
It's useful to be able to do equality tests for these for unit tests. Should we do this more consistently?
Uses a conditional compilation selector set by modern compiler versions for code gated behind a target architecture.
I am working on providing support for interrupt dispatching in vectored mode. This is a first draft, and I could not test yet if it works. However, I wanted to...
 Are there any plans to provide support for platform specific extensions in `riscv` crate? Reading through *RISC-V Privileged Architectures* specification I see that there are cases where, for example,...
The default `fence` instruction with no parameters is the strongest form of barrier. But it also takes an optional set of flags to give fine-grained control over exactly what operations...
As far as I understand the crates can be compiled with S-mode support, but in that case the assumption will be that it starts and always runs in S-mode. Is...
Demo repo: https://github.com/dreiss/panic_repro . It's a fairly simple riscv-rt example targeting riscv64 on qemu. On "rustc 1.78.0-nightly (a84bb95a1 2024-02-13)" or later, the link fails with bad relocations in eh_records: ```...
Motivated by #179 (and #180), I took a look on how the `cortex-m` crate deals with [assembly instructions](https://github.com/rust-embedded/cortex-m/blob/master/cortex-m/src/asm.rs), and most of them are safe and use options to avoid the...